In many electronic systems, especially those involving pulse and digital techniques, the need arises to generate a signal having a period which is some multiple, not necessarily an integer, of a given (periodic) signal. Heretofore, such frequency division or synthesis has employed locked oscillators or phase-locked loops.
However, in some cases it is sufficient that the average period of the synthesized signal be some large non-integral multiple of the given signal's period. In this event, other structural arrangements may be more suitable.
For example, given a periodic signal having a rate R and a period 1/R, it is desired to generate another signal whose period P is .lambda./R where .lambda.&gt;1. If .lambda. is an integer N, it is sufficient to load a down-counter with the value N and clock it at the rate R. At the counter's terminal count (zero), an output is produced which is used to reload the counter with N. The terminal count (TC) signal thus has a period NP, as desired.
In order to increase the period it is necessary to load the counter with a larger value. If the larger value is N+1 and this value is loaded L times while N is loaded M times, then for (L+M) terminal counts the number of input pulses will be L(N+1)+M(N)=N(L+M)+L, and the average TC period will be 1/(L+M) times this value, multiplied by P, that is P(N+L/(L+M).
Thus, for example, if L+M=10, average fractional frequency division to an accuracy of one part in 2(10N+L) can be obtained.